Author: He Tingbo, Semiconductor Industry Insights

After six years of research and development, Huawei has completed the mass production of 381 chips.

At ISCAS 2026, He Tingbo of Huawei delivered a keynote speech entitled "Exploration and Practice of New Paths in Semiconductors," in which he introduced a new principle guiding the development of the semiconductor industry—the T Law—aimed at solving the physical and economic dilemmas facing Moore's Law.

The full details of the presentation will be published in SCIENCE CHINA Information Sciences under the title "A Time Scaling Theory for Multi-Layer Electronic Systems".

summary

For six decades, Moore's Law's geometric shrinking has driven the semiconductor industry's continuous development. However, this paradigm has become ineffective: the technological benefits of simply reducing chip size are dwindling, the design cost of a single cutting-edge chip has exceeded one billion US dollars, and the cost of a single transistor in advanced processes has stopped decreasing. This paper proposes a time scaling criterion (τ scaling) as a new development paradigm, abandoning transistor area as the core measure of technological progress and instead defining time itself as the core indicator. This criterion uses a unified characteristic time constant τ as the optimization target, covering a range of 12 orders of magnitude from transistor switching actions to data center workloads.

The article showcases two mass-production-ready technology examples: In mobile system-on-a-chip (SoC), logic folding technology arranges digital, analog, and memory circuits in a vertically stacked active layer, achieving a 55% increase in transistor density and a 41% improvement in energy efficiency under a fixed process. In the field of artificial intelligence systems, a collaborative design system integrating a unified bus architecture for memory semantics, encapsulated short-range high-speed optoelectronic interconnect interfaces, and 3D stacking folding technology is expected to achieve a more than 100-fold increase in hardware integration by 2035. From a methodological perspective, τ-scaling is the first technical principle, after Dennard scaling, that can be applied across the entire computing architecture to establish a unified optimization goal.

introduction

Since the mid-1960s, the semiconductor industry has consistently measured technological iteration in nanometer dimensions. The industry has maintained a pace of development where transistor size shrinks, operating frequency increases, and the cost per logic gate decreases every 18 months. Moore's Law is both an objective industry law and a foundational consensus supporting the development of the entire computing system.

This consensus no longer holds true. With the advent of 7nm and below process technologies, the reduction in geometric dimensions can no longer replicate the technological gains of the past. Photolithography processes are approaching the physical limits of patterning, and the depreciation costs of extreme ultraviolet (EUV) lithography equipment constitute a large portion of wafer manufacturing costs. The cost of single transistors has stagnated or even rebounded. For companies unable to acquire top-tier lithography equipment, the limitations on development become apparent earlier, and the pressure on the industry is more severe.

The core development proposition of the industry has thus shifted; it is no longer about exploring how small transistors can be made, but about clarifying the optimization targets and development goals.

Over the past six years, Huawei's semiconductor team has conducted full-chip-level technology research based on mobile SoCs, AI accelerators, system interconnect architectures, and packaging technologies. The research concludes that technological breakthroughs do not rely on entirely new process nodes or transistor architectures, but rather on reconstructing core optimization directions. This article argues that the evolution of electronic systems in the next decade will move beyond geometric scaling and enter a new phase of time scaling. From picosecond-level transistor switching responses to second-level data center task processing, all levels of the computing architecture will achieve systematic reduction around the characteristic time constant τ.

This article, drawing on the R&D experience of 381 chips that have been mass-produced and deployed from May 2020 to May 2026, explains the τ scaling technology system from two dimensions: scientific methodology and industrial roadmap.

I. The era of geometric scaling comes to an end

The core task of the semiconductor industry has long been to continuously shrink the size of transistors. In 1965, Gordon Moore proposed that transistor density would roughly double every two years. Ten years later, Robert Dennard proposed the scaling theory, which proved that voltage and size could be reduced proportionally while maintaining a stable electric field strength.

Over the past fifty years, the combination of geometric scaling and Dennard scaling has enabled exponential improvements in chip performance per unit power consumption and per unit cost.

This development paradigm collapsed in two phases: Around 2005 : Denard scaling failed first, voltage no longer decreased proportionally with feature size, and the dark silicon era of chips began; After the 7nm node : the geometric scaling dividends, which relied on FinFET and gate-all-around (GAA) architectures, completely peaked. The core reasons have become an industry consensus: the speed saturation effect caused intrinsic delay to change from a quadratic correlation with channel length to a linear correlation; parasitic resistance and capacitance of local interconnects gradually dominated the delay budget of standard cells; mask costs, EUV depreciation, and design rule complexity soared, and the design budget for a single top-tier chip at the 2nm node exceeded $1 billion.

The economic aspect is equally unavoidable: the cost of single transistors in advanced processes has stagnated, and the cost of top-level nodes has even increased; the industry logic that has sustained fifty years of more transistors and lower costs per generation has completely collapsed.

For Huawei Semiconductor, the limitations of advanced lithography equipment, coupled with the fact that the geometric route has reached its peak, are forcing us to confront the fundamental problem that the entire industry will eventually face: we must break free from process node dependence and reconstruct the underlying technology evolution logic.

Second, the core of development has shifted from space to time, returning to the essence of Moore's Law.

From the perspective of actual user experience, the core of Moore's Law has never been about size. As transistors become smaller, switching response speeds increase; interconnects become more compact, signal transmission distances shorten; and as integration levels increase, data interaction boundaries decrease.

The essence of each generation of chip iterations is to continuously compress operating time: at the device level, the time span is from picoseconds to nanoseconds; at the chip level, it's from nanoseconds to microseconds; and at the system level, it's from microseconds to seconds. Reducing spatial size is merely a means to compress operating time.

Based on this core logic, the industry optimization approach has undergone a complete transformation, establishing time as the core metric. Characteristic time constants τ can be defined at each level—transistor, circuit, chip, and system—and reducing τ is set as a unified optimization objective. Geometric scaling becomes only one of the means to reduce time loss.

This paper defines this criterion as τ-time scaling , as a new underlying theory succeeding Moore's geometric scaling and leading the evolution of the semiconductor industry. The characteristic time constant satisfies a hierarchical functional relationship:

The time constant of each level is composed of the underlying time consumption of the lower level, plus the architecture and communication interaction losses of the current level. The time span of τ covers picoseconds to seconds, and the spatial span covers nanometers to kilometers. The technical approaches to reducing τ at each level have different focuses:

Transistor level : Optimize inherent switching delay by improving carrier mobility, stress process, high dielectric constant metal gate, and gate all-around architecture, while reducing local interconnect parasitic resistance and capacitance parameters;
Circuit hierarchy : Optimize signal transmission impedance-capacitance delay, use low-resistance wires and low-dielectric materials, and shorten wiring length by relying on vertical integration;
Chip-level : Reduce computation and memory access latency through optimization of architecture design, pipeline configuration, memory hierarchy and on-chip interconnect network;
System level : Compress end-to-end data transmission and synchronization time, and optimize interconnection topology, communication protocols and network architecture.

This leads to the following generational iteration pattern for chips: the time constant of the next generation equals the current time constant divided by a scaling factor. The scaling factor varies depending on the application scenario: approximately 1.3 times annually for power-constrained mobile devices; approximately 1.5 times for high-reliability autonomous driving systems; and up to 10 times for AI businesses where computing power directly determines economic benefits.

The τ metric can coordinate the entire computing architecture. Performance parameters such as frequency, latency, bandwidth, and throughput are essentially determined by the τ metric at the corresponding level. Process development, circuit design, and system architecture personnel can collaboratively optimize based on a unified metric, thus ending the development model of independent optimization at each level and post-event accounting of timing losses.

III. Logical Folding: Empirical Evidence of Mobile SoC Technology

The τ-scaling technology has been deployed and tested on a large scale in a mobile scenario for the first time. Smartphone SoCs are unique, with a single chip constituting the entire device system. These devices cannot perform parallel processing across multiple slots, nor do they have an interconnected architecture with thousands of nodes to offset link latency. All performance output is achieved on a single die, consuming only a few watts of power, while also being constrained by the heat dissipation limitations imposed by the device's form factor.

After 2020, access to advanced manufacturing processes became limited, and the industry faced a core problem: how to continuously achieve generational performance upgrades for single chips when process technology was no longer iterated?

Logical folding technology was thus developed.

Definition : Logic folding is a design scheme that follows the time scaling principle, splitting digital circuits, analog circuits, and memory circuits into multiple layers of vertically stacked active chips to optimize chip performance, power consumption, and area.

Digital circuits are divided into two categories: combinational logic and sequential logic. Combinational logic refers to Boolean operation circuits between registers, while sequential logic consists of flip-flops responsible for storing states. The upper limit of digital system performance is determined by the critical path delay between adjacent flip-flops, and the delay is mainly affected by the parasitic RC parameters of the circuit and the number of gate circuits in the path. Traditional designs lay the gate circuits flat on the same plane, and the wiring is completed by relying on the upper metal layer; the longer the wiring length, the higher the parasitic RC losses, and the slower the critical path runs.

Logic folding breaks away from planar design thinking, splitting and arranging critical path gate circuits into two or more vertically stacked active chip layers, and completing inter-layer interconnection through ultra-fine pitch hybrid bonding technology.

From a circuit design perspective, multilayer chips can be viewed as a unified, complete architecture, with components distributed across layers, effectively equivalent to adding new metal wiring layers. Signal trace lengths are significantly reduced, parasitic resistance and capacitance losses are substantially decreased, clock skew is optimized, and chips can achieve higher clock frequencies using the same manufacturing process.

To fully leverage the performance advantages of logic folding, the ratio of hybrid bonding pitch to top metal pitch should be kept low, ideally below 3 in practice. A lower ratio generally results in better overall performance. Currently, the top metal pitch is approximately 720 nanometers, corresponding to a hybrid bonding pitch that needs to be controlled within 2 micrometers. Ideally, the ratio should approach 1, completely eliminating wiring redundancy losses at the bonding interface.

Achieving this bonding pitch while simultaneously meeting the requirements of overlay accuracy of less than 0.5 micrometers, aperture and isolation area of less than 1.5 micrometers, and through-silicon via specifications of less than 6 micrometers pitch, as well as production requirements that approach full yield by relying on intelligent redundancy technology, has been achieved through years of process research and development across the entire industry chain.

The 2026 Kirin chip has achieved several substantial results in real-world testing:

Transistor density increased in a stepwise manner from 155 MTr/mm² (million transistors per square millimeter) to 238 MTr/mm² in a single generation (the formula for calculating transistor density is:

The Kirin SoC design has an area utilization rate of 68% – an improvement that previously required three years of geometric miniaturization to achieve.

The SoC's core energy efficiency is improved by 41%, and the maximum clock speed increases by nearly 13%.
By constructing a high-speed on-chip network data path across two layers, the path area is reduced by 55%, and the power supply stability is improved simultaneously.
The post-silicon clock skew optimization scheme independently contributes over 5% to the overall chip performance increase.
The critical path of static random access memory is shortened, the energy consumption per bit is reduced, the operating frequency is increased by more than 40%, and the storage read/write speed, energy consumption and area indicators are comprehensively optimized.
The mainstream computing core adopts a two-layer folded architecture, which reduces the number of clock buffers by more than 50%, reduces clock skew by 25%, and reduces wiring length by about 30%.

The aforementioned performance improvements were all achieved within the existing process nodes, without employing any new lithography process, and were realized by reconstructing the logic circuit layout in three-dimensional space.

The logic folding technology featured in the 2026 Kirin chip adopted a conservative implementation approach: the hybrid bonding pitch was 1.5 micrometers, the through-silicon via (TSV) contacts were only moved one layer below the top metal layer, and the folding technology was only applied to core critical paths, not implemented across the entire chip. Even so, the CPU core frequency still rebounded to 3.1 GHz this year.

Over the next decade, logic folding will gradually evolve from localized critical path folding to global multi-layer folding, with single packages capable of stacking three, four, or more active chip layers. Low-temperature hybrid bonding technology can relax multi-layer heat dissipation limitations, and by moving through-silicon via (TSV) contacts down to the sixth metal layer, over 30% of high-layer wiring resources can be freed up.

Between 2026 and 2035, transistor density is expected to exceed 400 million transistors per square millimeter. Logic folding technology will help Kirin chips significantly increase CPU core clock speeds, gradually moving towards 4 gigahertz and higher frequencies. This technological approach is feasible and has economic advantages in terms of commercialization costs.

Kirin chip performance core frequency iteration trend

Logical folding core parameters

Hybrid bonding pitch: less than 2 micrometers, mass production version 1.5 micrometers, target pitch ratio 1:1
Overlay accuracy: less than 0.5 micrometers
Through-Silicon Vias (TSV) Specifications: Critical dimensions, isolation area less than 1.5 micrometers, spacing less than 6 micrometers.
Yield: Intelligent redundancy design achieves near-full yield.
Transistor density: 55% increase per generation
Performance and energy efficiency, and clock speed: improved by 41% and 13% respectively.
Static storage clock speed: increased by over 40%
Core unit loss metrics: Clock buffer halved, skew reduced by 25%, wiring shortened by 30%.

IV. Picosecond to Microsecond Optimization: T-Scaling Applications in AI Data Centers

After verifying the feasibility of the technology in low-power scenarios on mobile devices, this principle also applies to ultra-high-power AI training and inference scenarios. AI clusters, consisting of tens of thousands of chips working collaboratively, have seen their overall computing power increase by six orders of magnitude over the past decade. By implementing the τ-scaling approach throughout the entire value chain, the technology can be successfully implemented.

The development of artificial intelligence systems is characterized by two main features: the continuous expansion of chip cluster scale; and the fact that system energy consumption and costs are primarily consumed by data transmission rather than computation. Large computing clusters consume over 80% of their energy for data interaction and over 70% of their costs are invested in storage devices. Therefore, reducing data transmission time within chips, racks, and packages is just as important as optimizing computation time.

AI scenario time scaling relies on three collaborative architectures: Unified Bus , Hi-ONE encapsulated near-field optical interconnect engine, and 3D Folding encapsulated topology reconstruction.

4.1 Unified Bus: A system interconnection architecture with time optimization as its core.

Traditional multi-chip acceleration systems have complex layered protocols, with different communication protocols used between the host, the chassis, and the rack. Protocol conversion, data caching, and interactive verification continuously increase latency, reduce stability, and drive up costs.

The unified bus architecture abandons the multi-layered protocol system and adopts a global peer-to-peer interconnection protocol, natively adapting to storage access logic. Data transmission requires no protocol conversion, relying on hardware to maintain data consistency, replacing the traditional software message interaction mode. Real-world testing shows that remote access latency has been reduced from tens of microseconds to 100 nanoseconds, and core communication link time loss has been reduced by approximately 500 times, enabling large-scale rack clusters to achieve integrated collaborative operation.

4.2 High-Density Optoelectronic Interconnect Engine: Package-Level High-Speed Optical Interconnect

After optimizing communication latency, new bottlenecks emerge: increased chip density in a single rack leads to power consumption density and reliability reaching physical limits, and the bandwidth of traditional electrical interconnect SerDes is also approaching its upper limit. At a single AI chip speed of 400Gb/s, copper interconnects remain reliable and usable; however, once the speed is increased to the Tb/s level, copper solutions become completely unfeasible: SerDes transmission distance drops sharply, cabling becomes bulky, rack installation becomes significantly more difficult, and heat dissipation and power supply margins are exhausted.

Huawei Semiconductor has proposed Hi-ONE, a high-density optical interconnect node engine : encapsulating near-field optical interconnect modules with a single-path bandwidth of up to 8Tb/s, precisely matching the bandwidth of the unified bus for AI chips. Technical benefits: SerDes transmission distance is reduced from approximately 100 cm to 5 cm, eliminating bulky copper cables; cross-rack transmission distance is extended from less than 1 meter to 100 meters, providing a physically feasible solution for high-density interconnection in gigawatt-scale hyperscale data centers.

The Hi-ONE design philosophy deeply aligns with the τ scaling concept: it abandons dedicated digital signal processors (DSPs) for high signal fidelity, adopting a linear architecture of analog equalization enhancement drivers + transimpedance amplifiers; it relaxes bit error rate tolerance, with a unified bus protocol adapting to fault-tolerant mechanisms. Through cross-layer trade-offs between the physical and protocol layers, it reduces power consumption, cost, and integration complexity, representing a typical practice of cross-layer collaborative optimization based on τ theory.

4.3 The Architectural Dilemma of N² and N: The Inevitability of Three-Dimensional Folding

AI accelerators cannot stop at 2.5D fan-out packaging. The underlying reason is geometric topological constraints , which directly determine the technology roadmap after 2030.

Traditional 2.5D AI chip architecture: The logic die is centered, with HBM memory stacks and SerDes interconnect interfaces arranged at the edges, and a voltage regulator module integrated on the periphery. All storage signals, interconnect signals, and power supply current must pass through the edge of the die to reach the internal computing unit.

Let the side length of the bare wafer be N:

Computing power is directly proportional to chip area, with a scale of N² .
Memory bandwidth, interconnect bandwidth, and power supply capability rely on edge fanout, with a scale of only N.

The gap between the increasing computing power and the linearly increasing bandwidth/power supply capacity continues to widen, creating a fan-out dilemma . Even with continuous iterations in logic technology, it is impossible to make up for the inherent shortcomings of the topology architecture, and transistor-level optimization cannot solve the physical constraints at the architecture level.

3D Folding breaks this deadlock: it migrates power supply (back-side power supply + integrated voltage regulator), high-speed memory (hybrid bonding layered integration), and optical interconnect I/O (Hi-ONE close-range integration), which were originally limited to the chip edge, to resources on the chip's vertical surface. Resource layout is upgraded from edge-surrounding to a full-domain three-dimensional distribution, with bandwidth, optical interconnects, and power supply capabilities simultaneously upgraded to N² growth, matching the growth rate of computing power. The packaging form is completely restructured: from a planar structure of logic die + edge peripherals, it is upgraded to a vertically integrated stack where logic, interconnects, memory, and power supply scale synergistically.

 AI technology roadmap timeline

Before 2030: Ascend SuperPoD relies on the mature technology iteration of chip, 2.5D fan-out, and micro-bump/standard pitch hybrid bonding three-dimensional stacking, with representative products being Ascend 910C in 2025, Ascend 950 in 2026, and the subsequent Ascend 990;
Around 2030: Ascend 990 will be the first to introduce logic folding into AI accelerators;
2030-2035: 3D folding becomes the core carrier of technological iteration, and hardware integration is expected to increase by more than 100 times ; τ optimization is fully distributed across all layers of the stack, no longer limited to the device process level.

Appendix: Core Metrics for AI System-Level Scaling

Unified bus remote access latency: tens of microseconds → 100 nanoseconds, τ reduced by approximately 500 times.
Hi-ONE single-module bandwidth: 8Tb/s, matching the unified bus bandwidth of a single chip.
Hi-ONE transmission distance: Intra-board SerDes 100cm → 5cm; Cross-rack 1m → 100m
Fan out of the dilemma: Computing power increases by N², while edge bandwidth/I/O/power supply only increases linearly by N.
The value of 3D folding: bandwidth, optical interconnects, and power supply migrate from the edge to the 3D surface, restoring N² synchronous scaling.
2026-2035 Outlook: Hardware Integration to Increase by Over 100 Times

V. Logic and Storage: From Separation to Deep Integration

The τ scaling criterion has also driven changes in the logic chip and memory chip industry landscape. In the early days, the industry used standardized buses and deliberately distinguished between processors and memory, with the two industries developing independently.

The era of artificial intelligence is breaking down the separation model, with the explosive growth of computing power constantly pushing the limits of storage bandwidth, latency, and packaging technology. High-bandwidth memory, hybrid bonding, and three-dimensional stacked storage technologies all demonstrate that data transmission is just as critical as computation, and logic and storage chips are moving towards physical integration. Industry power is gradually shifting towards storage and packaging companies.

Technological convergence is an inevitable trend, but the distribution of industry benefits is still undefined. Future winners in the hardware field will achieve deep integration of logic and storage technologies and build a long-term, mutually beneficial cooperation system. τ-scaling directly reflects the losses caused by layered separation, forcing the industry to address structural integration issues as soon as possible.

VI. Existing Technological Challenges

The τ scaling system is still in the improvement stage, and many key challenges need to be overcome. At the same time, we are also seeking technical cooperation from the entire industry.

EDA Toolchain and Design Methodology: Existing EDA tools were developed for the era of planar design, with independent optimization of area, timing, and power consumption, and the system τ was a passive result. Full-scale logic folding requires the toolchain to treat multi-layer stacked dies as a single continuous design unit, supporting unit-level cross-layer partitioning, globally unified cost function placement and routing, and inter-layer timing convergence; it also needs to take into account scenarios that traditional two-dimensional tools cannot adapt to, such as vertical interconnect parasitic parameters, forbidden area occupancy, and wafer-to-wafer process deviations. Huawei has developed a preliminary toolchain, and the methodology details will be publicly released later; an open-source EDA toolchain for τ-native, multi-physics, and three-dimensional architectures is the most core foundational investment for the next decade.

Inter-wafer process deviations: Logic folding can be achieved by bonding and stacking wafers from different batches or even different process nodes. Deviations in threshold voltage, drive current, and interconnect RC parameters between wafers are far greater than those within a single wafer, significantly impacting clock distribution and timing margin maintenance. A complete solution needs to be established based on intelligent redundancy, adaptive compensation, and a τ-aware approval process.

Vertical interconnect losses : Hybrid bonding and through-silicon vias (TSVs) inherently possess parasitic resistance and capacitance losses, and TSV forbidden zones occupy standard cell layout area. Logic folding implementation must meet the core criterion: τ<sub>gain</sub> (effective chip area + wiring length reduction) > τ<sub>loss</sub> (vertical interconnect RC parasitics). Current critical paths and storage scenarios have already exceeded the gain threshold; the threshold boundary is continuously optimized as bonding spacing decreases, and it adapts to differentiated judgment standards for different business loads.

Energy Constraints: τ is a time-based criterion, not an energy-based one. A 10x speedup in architecture accompanied by a 10x increase in power consumption, while not violating the τ scaling principle, would exceed the grid's power supply capacity. Therefore, τ scaling must be accompanied by an energy optimization system: eliminating protocol stack overhead with a storage semantic bus, reducing single-bit energy consumption by several orders of magnitude through encapsulated near-field optical interconnects, back-side power supply, in-memory/near-memory computing, and data center-level dynamic frequency and voltage regulation (DVFS); utilizing the τ timing margin to inversely trade off power gains, achieving a two-way balance between latency and energy consumption.

Benchmarking System: Existing industry performance benchmarks (Linpack, MLPerf, SPEC) are designed for single-metric evaluation and cannot meet the needs of full-stack optimization with τ scaling. There is an urgent need to build a τ profile benchmark system to quantify the dominant latency and optimization margin at each level of the system and accurately identify the core investment levels for the next stage.

VII. Six years of R&D accumulation, looking ahead to ten years of development

From May 2020 to May 2026, Huawei Semiconductor has completed the mass production of 381 chips for mobile, AI, automotive, industrial, and infrastructure sectors. The entire product matrix verifies the validity of the τ-time scaling theory: At the device circuit level, the transistor density is expected to exceed 400 million per square millimeter by 2031; at the chip level, under fixed process technology, the clock speed, energy efficiency, and integration will be continuously improved by logic folding; at the system level , communication latency will be reduced from microseconds to nanoseconds, and large-scale computing clusters will achieve integrated collaboration; in terms of industry outlook, the chip clock speed will reach 4 gigahertz by 2029, the energy efficiency of mobile chips will double within three to five years, and the integration of artificial intelligence hardware will increase a hundredfold by 2035.

Compared to product iteration, the methodological innovation brought about by τ scaling has far-reaching significance. This is the first unified standard for optimizing the entire computing architecture since Denard's Law, enabling process, circuit, architecture, and software teams to collaboratively upgrade around the same metric. Simultaneously, the logic of industry competition is shifting; it's no longer necessary to simply pursue cutting-edge lithography processes; packaging, memory bandwidth, and interconnect architecture have become core competitive advantages.

The long-held industry perception that equates Moore's Law reduction with technological advancement is undergoing a major shift. The era of geometric scaling has ended, and performance leaps achieved through time optimization in multi-layered architectures have become the new direction. In the next six to ten years, companies and ecosystems with τ-scaling as their core development goal will dominate the next generation of the computing industry landscape.

The road ahead for industrial development is fraught with challenges, but the direction of evolution is clear and definite. Various technical challenges cannot be overcome by a single company; design tools, industry standards, device physics, and business models all require collaborative efforts from the entire industry. This article is both a summary of technical practices and a sincere invitation to industry colleagues to explore and move forward together.

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